Special Manpower Development Program in VLSI Design & Related Software Phase-II (SMDP-II)

Major elements of the program were:-

  1. Establishing State of-the art VLSI Design Laboratory.
  2. Generation of manpower in VLSI Design area at various levels.
  3. Instruction Enhancement Program (IEP) for faculties of PIs.
  4. Workshop involving International Guest Faculty.
  5. India Chip Program.
  6. National VLSI website and 7 sites at RCs.

Objectives

  • Primary Objective - To train special manpower in the area of VLSI Design and related software at M.E./M.Tech level (Type-II manpower). In addition to this, generation of Type-III manpower i.e. M.E./M.Tech in other areas of electronics etc. with at least two courses on VLSI design was also undertaken.
  • Secondary Objective - Train Type-IV manpower i.e. B.E./B.Tech in electronics etc. with graduate level courses on VLSI Design. However, the program was not only limited to generation of Type-II, III & IV manpower but also generated manpower at Ph.D level in various aspects of VLSI design/microelectronics (Type-I manpower). The establishment of VLSI design laboratories at RCs would also strengthen their academic program.

Project Details:

  • Total Outlay: Rs. 49.98 Crores (Actual Expenditure: Rs. 42.24 Crores)
  • Duration- 8 Years (2005-2013)
  • Implementing Organizations:
    1. 7 Resource Centers (including 5 IITs, IISc Bangalore and CEERI Pilani)
    2. 25 Participating Institutes ( including 16 NITs and 9 other institutions).

The 32 implementing organizations were categorized as Resource Centres(RC) and Participating Institutions(PI). The PIs were mentored by the RCs by forming small groups as shown in figure below:

Achievements against major elements of the programme:

  1. Establishing State of the art VLSI Design Laboratory
  2. VLSI Design Laboratories have been established at 32 institutions equipped with State-of-the art Hardware platforms and Electronics Design Automation (EDA) software. These Labs are being use by students at various levels to undertake design of VLSI circuits. The license of EDA tools like Mentor Graphics & Synopsis have been renewed and the process for renewal of license in case of other EDA tools are in progress.

  3. Generation of manpower in VLSI Design area at various levels
  4. Under the program the students of RCs and PIs at various levels such as B.Tech, M.Tech and Ph.D where introduced to specialized topic in VLSI design. A model curriculum was also developed. The primary target of the program was to generate substantial number of manpower at M.Tech level having VLSI design as their primary specialization. Students at B.Tech level as well as M.Tech in other area of were also offered electives with VLSI and micro-electronics subjects. The manpower generated under this programme at various levels are depicted in table-1 below:

Table-1

Category 2005-06 2006-07 2007-08 2008-09 2009-10 2010-11 2011-12 2012-13 Total
Type-IV 2455 2773 3285 3845 3889 3867 3798 90 402
Type-III 564 680 739 717 809 886 980 622 3924
Type-II 301 339 442 456 613 550 601 1064 6439
Type-I 24 40 39 49 54 49 67 4268 28170
Total 3344 3832 4505 5067 5365 5352 5446 6044 38935
Type-I:Ph.D in various aspects of VLSI Design & CAD
Type-II: M.E./M.Tech in VLSI Design & CAD
Type-III:M.E./M.Tech in other areas of Electronics/ Communication/Computer Science/ Instrumentation etc. who have taken at least two courses on various aspects of VLSI Design & CAD
Type-IV:B.E./B.Tech in Electronics/ Computer Science/ Communication / Instrumentation etc. who have taken courses on VLSI Design & CAD

India Chip Program:

Fabrication of twelve chips, 5 in single mode and 7 in multi-mode project wafer (MPW) mode were undertaken for siliconisation of Analog and Digital designs done by students of various RCs and PIs. In the seven MPW chips 32 designs from 16 institutions were integrated together and were prototyped in seven chips. For the seven chips there were seven institutions which acted like an integrator to merge the designs received from other institutors. In this way there was considerable savings in the fabrication cost.

Chip Layout views of integrated designs under India Chip Programme



Instruction Enhancement Program (IEP) for faculties of PIs-

Twenty three Instruction Enhancement Programme (IEP) in different topics/area were conducted at various RC/PI locations by Resource centers for the training faculty of Participating Institutions. A total of 654 faculties/Lab Engineers of PIs have been trained through this programme. The details are as below:

S. No Name of the Institute Date Topic Participants Attended
1. IIT Kanpur July 3 - 14, 2006 Digital IC Design 21
2. IIT Kharagpur Sep 11 - 23, 2006 Low Power VLSI Design 24
3. IIT Madras Nov 13 - 24, 2006 RF IC Design 27
4. IISc. Bangalore Dec 4 - 15, 2006 Semiconductor Device Modeling & Simulation 18
5. IIT Delhi July 2 - 13, 2007 Analog IC Design 27
6. IIT Kharagpur Sep 24 - Oct 5, 2007 VLSI-DSP based design 27
7. IIT Kanpur Dec 10 - 21, 2007 Synthesis of Digital System 25
8. IISc. Bangalore Mar 10 - 19,2008 VLSI Testing & Verification 24
9. IIT Kharagpur May 12 - 17, 2008 Technology CAD 11
10. CEERI Pilani Oct 14 - 18, 2008 Linux System Administration and EDA Tools Installation 26
11. GEC Goa (Conducted by IIT Bombay) Mar 16 - 21, 2009 Mixed-Signal VLSI Design 33
12. IIT Delhi July 13 - 18, 2009 FPGA Laboratory 15
13. Thapar University, Patiala (Organised by CEERI Pilani) Dec 14 - 23, 2009 System Modeling Using System C/VHDL/Verilog 17
14. IIT Madras Feb 22 - 26, 2010 Algorithms to Architectures 17
15. IIT Kharagpur Mar 2 - 13, 2010 Low-Power,High Speed Digital Subsystem Design : Spec to Test 14
16. NIT Trichy (Organised by IIT Madras) Sep 29 - Oct 2, 2010 Chip Integration and Tapeout Issues 27
17. MNIT Jaipur (Organised by CEERI Pilani) Dec 13 - 17, 2010 Semiconductor Memory Design & Test 52
18. IIT Kharagpur Mar 6 - 12, 2011 VLSI aspects on Biomedical Engineering 22
19. IIT Delhi Mar 14 - 19, 2011 Low Power, Low Noise, Operational Amplifier Design 20
20. VNIT Nagpur (Organised by IIT Bombay) Oct 8 - 10, 2011 Design Finishing for Chip Tape Out 25
21. IIT Madras, IISc. Bangalore, IIT Delhi Dec 9 - 12, 2011 Analog/ Mixed Signal Design 50
22. IIT Delhi Jan 16 - 19, 2012 RFIC & System Design 20
23. IIT Kanpur Sep 24 - 28, 2012 Low Power Digital Design 24