MeitY in collaboration with Mentor Graphics is offering training opportunities for the students of institutions involved in the SMDP-C2SD Programme to generate industry-ready manpower promoting industry-academia interaction.
The trainees will be able to learn the complete design cycle (starting from design specifications to fabrication of chips) for development of SoCs/ Systems, ASICs and FPGAs based designs.
Eligibility: Final year B.E/B.Tech (Electronics/Electrical) students having sufficient time left for completion of their training.
How to Apply: Eligible students should directly register themselves on www.mentor.com/systemverilog-training as provided in the Mentor Graphics Training flyer before the last date i.e 20th May 2019.
Details on Training start date, location, etc. will be communicated in due course of time. Additional details can be had from the contact point mentioned in the flyer.