Call for Designs from Institutes other than SMDP-C2SD Institutes seeking support for Fabrication in SCL 180nm Technology

Criteria for selection of 10 best designs from amongst the submitted designs from institutes other than SMDP-C2SD institutes for fabrication in SCL 180nm technology under SMDP-C2SD Program

Details of the institution and faculty in charge for the design to be fabricated(ResearchInterest, Prior experience with chip tapeouts and related publications/theses/reports, name of mentor/ guide (in case of student) etc).


Description of the research project (Bachelor's/ Master's/ Ph.D) of which the design is part of:

a.    Timelines, design closure/tape out date of the design.

b.    The details of faculty/ students participated and their contributions in the design.

c.    Explain briefly the role/interest of external collaborators or stakeholders, if any, in the research project (of the which the design is part of) or the design to be fabricated.


Description of the design to be fabricated:

a.    Specifications (architecture/design/interfaces/ features etc.)

b.    Functionality

c.    Application

d.    Description of various Sub-blocks/ Sub-modules/ IPs in the design to be fabricated.


Briefly justify why the design should be selected for fabrication:

a.   Highlights of proposed novelty in the design (in terms of performance/area/power/features/specifications etc.)vis-à-vis state of the art available in the market.

b.    What is the expected outcome of proposed fabrication (paper, technical report, thesis, identified application etc.)

c.    Whether/ how this design to be fabricated likely to spawn-off further work/projects of interest and what are the challenges anticipated?

d.    Whether/ how the design to be fabricated has societal/ strategic application?

e.    Whether/ how the design to be fabricated can result in import substitution?

f.     Whether/ how the design to be fabricated have export potential?

g.    Whether/ how the design will help further to train the students?


Test plan for testing the chip including the details on availability of test PCB/ lab equipment for testing/ packaging plan/ timelines of testing.


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