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About
SMDP-I
SMDP-II
SMDP-C2SD
SMDP-C2SD
Institutes
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International Guest Faculty Lectures
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Patents Filed
ASICs Fabricated
SoCs Designed
VLSI Design Labs
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Instruction Enhancement Programmes (IEP)
Mixed Signal SoC - from design to tapeout (hands-on)
S.No
Topic Name
1
Day1 - Inauguration
2
Day1 - Overview
3
Day1 - VBox Virtuoso sch ADE L XL
4
Day1 - Virtuoso layout DRC LVS PEX
5
Day2 - Standard Cell basics layout liberty
6
Day2 - SCL - Part1
7
Day2 - SCL - Part2
8
Day2 - Liberate & Abstract
9
Day3 - Verilog AMS
10
Day3 - Sys Verilog MSP430 basics
11
Day4 - RTL to GDSII part1
12
Day4 - RTL to GDSII part2
13
Day5 - RTL to GDSII final
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